at91_us.h File Reference

---

Detailed Description

AT91 peripherals.

 *
 * $Log: at91_us.h,v $
 * Revision 1.3  2006/08/31 19:12:43  haraldkipp
 * Added additional registers found on the AT91SAM9260.
 *
 * Revision 1.2  2006/08/05 11:55:30  haraldkipp
 * PDC registers are now configurable in the parent header file.
 *
 * Revision 1.1  2006/07/05 07:45:28  haraldkipp
 * Split on-chip interface definitions.
 *
 *
 * 

USART Control Register
#define	US_CR_OFF   0x00000000
	USART control register offset.
#define	US0_CR   (USART0_BASE + US_CR_OFF)
	Channel 0 control register address.
#define	US1_CR   (USART1_BASE + US_CR_OFF)
	Channel 1 control register address.
#define	US_RSTRX   0x00000004
	Reset receiver.
#define	US_RSTTX   0x00000008
	Reset transmitter.
#define	US_RXEN   0x00000010
	Receiver enable.
#define	US_RXDIS   0x00000020
	Receiver disable.
#define	US_TXEN   0x00000040
	Transmitter enable.
#define	US_TXDIS   0x00000080
	Transmitter disable.
#define	US_RSTSTA   0x00000100
	Reset status bits.
#define	US_STTBRK   0x00000200
	Start break.
#define	US_STPBRK   0x00000400
	Stop break.
#define	US_STTTO   0x00000800
	Start timeout.
#define	US_SENDA   0x00001000
	Send next byte with address bit set.
Mode Register
#define	US_MR_OFF   0x00000004
	USART mode register offset.
#define	US0_MR   (USART0_BASE + US_MR_OFF)
	Channel 0 mode register address.
#define	US1_MR   (USART1_BASE + US_MR_OFF)
	Channel 1 mode register address.
#define	US_CLKS   0x00000030
	Clock selection mask.
#define	US_CLKS_MCK   0x00000000
	Master clock.
#define	US_CLKS_MCK8   0x00000010
	Master clock divided by 8.
#define	US_CLKS_SCK   0x00000020
	External clock.
#define	US_CLKS_SLCK   0x00000030
	Slow clock.
#define	US_CHRL   0x000000C0
	Masks data length.
#define	US_CHRL_5   0x00000000
	5 data bits
#define	US_CHRL_6   0x00000040
	6 data bits
#define	US_CHRL_7   0x00000080
	7 data bits
#define	US_CHRL_8   0x000000C0
	8 data bits
#define	US_SYNC   0x00000100
	Synchronous mode enable.
#define	US_PAR   0x00000E00
	Parity mode mask.
#define	US_PAR_EVEN   0x00000000
	Even parity.
#define	US_PAR_ODD   0x00000200
	Odd parity.
#define	US_PAR_SPACE   0x00000400
	Space parity.
#define	US_PAR_MARK   0x00000600
	Marked parity.
#define	US_PAR_NO   0x00000800
	No parity.
#define	US_PAR_MULTIDROP   0x00000C00
	Multi-drop mode.
#define	US_NBSTOP   0x00003000
	Masks stop bit length.
#define	US_NBSTOP_1   0x00000000
	1 stop bit
#define	US_NBSTOP_1_5   0x00001000
	1.5 stop bits
#define	US_NBSTOP_2   0x00002000
	2 stop bits
#define	US_CHMODE   0x0000C000
	Channel mode mask.
#define	US_CHMODE_NORMAL   0x00000000
	Normal mode.
#define	US_CHMODE_AUTOMATIC_ECHO   0x00004000
	Automatic echo.
#define	US_CHMODE_LOCAL_LOOPBACK   0x00008000
	Local loopback.
#define	US_CHMODE_REMOTE_LOOPBACK   0x0000C000
	Remote loopback.
#define	US_MODE9   0x00020000
	9 bit mode
#define	US_CLKO   0x00040000
	Baud rate output enable.
Status and Interrupt Register
#define	US_CSR_OFF   0x00000014
	USART status register offset.
#define	US0_CSR   (USART0_BASE + US_CSR_OFF)
	Channel 0 status register address.
#define	US1_CSR   (USART1_BASE + US_CSR_OFF)
	Channel 1 status register address.
#define	US_IER_OFF   0x00000008
	USART interrupt enable register offset.
#define	US0_IER   (USART0_BASE + US_IER_OFF)
	Channel 0 interrupt enable register address.
#define	US1_IER   (USART1_BASE + US_IER_OFF)
	Channel 1 interrupt enable register address.
#define	US_IDR_OFF   0x0000000C
	USART interrupt disable register offset.
#define	US0_IDR   (USART0_BASE + US_IDR_OFF)
	Channel 0 interrupt disable register address.
#define	US1_IDR   (USART1_BASE + US_IDR_OFF)
	Channel 1 interrupt disable register address.
#define	US_IMR_OFF   0x00000010
	USART interrupt mask register offset.
#define	US0_IMR   (USART0_BASE + US_IMR_OFF)
	Channel 0 interrupt mask register address.
#define	US1_IMR   (USART1_BASE + US_IMR_OFF)
	Channel 1 interrupt mask register address.
#define	US_RXRDY   0x00000001
	Receiver ready.
#define	US_TXRDY   0x00000002
	Transmitter ready.
#define	US_RXBRK   0x00000004
	Receiver break.
#define	US_ENDRX   0x00000008
	End of receiver PDC transfer.
#define	US_ENDTX   0x00000010
	End of transmitter PDC transfer.
#define	US_OVRE   0x00000020
	Overrun error.
#define	US_FRAME   0x00000040
	Framing error.
#define	US_PARE   0x00000080
	Parity error.
#define	US_TIMEOUT   0x00000100
	Receiver timeout.
#define	US_TXEMPTY   0x00000200
	Transmitter empty.
#define	AT91_US_BAUD(baud)   ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
	Baud rate calculation helper macro.
Receiver Holding Register
#define	US_RHR_OFF   0x00000018
	USART receiver holding register offset.
#define	US0_RHR   (USART0_BASE + US_RHR_OFF)
	Channel 0 receiver holding register address.
#define	US1_RHR   (USART1_BASE + US_RHR_OFF)
	Channel 1 receiver holding register address.
Transmitter Holding Register
#define	US_THR_OFF   0x0000001C
	USART transmitter holding register offset.
#define	US0_THR   (USART0_BASE + US_THR_OFF)
	Channel 0 transmitter holding register address.
#define	US1_THR   (USART1_BASE + US_THR_OFF)
	Channel 1 transmitter holding register address.
Baud Rate Generator Register
#define	US_BRGR_OFF   0x00000020
	USART baud rate register offset.
#define	US0_BRGR   (USART0_BASE + US_BRGR_OFF)
	Channel 0 baud rate register address.
#define	US1_BRGR   (USART1_BASE + US_BRGR_OFF)
	Channel 1 baud rate register address.
Receiver Timeout Register
#define	US_RTOR_OFF   0x00000024
	USART receiver timeout register offset.
#define	US0_RTOR   (USART0_BASE + US_RTOR_OFF)
	Channel 0 receiver timeout register address.
#define	US1_RTOR   (USART1_BASE + US_RTOR_OFF)
	Channel 1 receiver timeout register address.
Transmitter Time Guard Register
#define	US_TTGR_OFF   0x00000028
	USART transmitter time guard register offset.
#define	US0_TTGR   (USART0_BASE + US_TTGR_OFF)
	Channel 0 transmitter time guard register address.
#define	US1_TTGR   (USART1_BASE + US_TTGR_OFF)
	Channel 1 transmitter time guard register address.
FI DI Ratio Register
#define	US_FIDI_OFF   0x00000040
	USART FI DI ratio register offset.
#define	US0_FIDI   (USART0_BASE + US_FIDI_OFF)
	Channel 0 FI DI ratio register address.
#define	US1_FIDI   (USART1_BASE + US_FIDI_OFF)
	Channel 1 FI DI ratio register address.
Error Counter Register
#define	US_NER_OFF   0x00000044
	USART error counter register offset.
#define	US0_NER   (USART0_BASE + US_NER_OFF)
	Channel 0 error counter register address.
#define	US1_NER   (USART1_BASE + US_NER_OFF)
	Channel 1 error counter register address.
IrDA Filter Register
#define	US_IF_OFF   0x0000004C
	USART IrDA filter register offset.
#define	US0_IF   (USART0_BASE + US_IF_OFF)
	Channel 0 IrDA filter register address.
#define	US1_IF   (USART1_BASE + US_IF_OFF)
	Channel 1 IrDA filter register address.

---