at91_mci.h File Reference

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Detailed Description

AT91 peripherals.

 *
 * $Log: at91_mci.h,v $
 * Revision 1.2  2006/09/05 12:32:13  haraldkipp
 * Timeout multiplier settings renamed to follow Atmel's convention.
 * 4-bit bus SDC setting corrected.
 * Several comments added or corrected.
 *
 * Revision 1.1  2006/08/31 19:10:37  haraldkipp
 * New peripheral register definitions for the AT91SAM9260.
 *
 *
 * 

MMC Control Register
#define	MCI_CR_OFF   0x00000000
	Control register offset.
#define	MCI_CR   (MCI_BASE + MCI_CR_OFF)
	Control register address.
#define	MCI_MCIEN   0x00000001
	Interface enable.
#define	MCI_MCIDIS   0x00000002
	Interface disable.
#define	MCI_PWSEN   0x00000004
	Power save mode enable.
#define	MCI_PWSDIS   0x00000008
	Power save mode disable.
#define	MCI_SWRST   0x00000080
	Software reset.
MMC Mode Register
#define	MCI_MR_OFF   0x00000004
	Mode register offset.
#define	MCI_MR   (MCI_BASE + MCI_MR_OFF)
	Mode register address.
#define	MCI_CLKDIV   0x000000FF
	Clock divider mask.
#define	MCI_CLKDIV_LSB   0
	Clock divider LSB.
#define	MCI_PWSDIV   0x00000700
	Power saving divider mask.
#define	MCI_PWSDIV_LSB   8
	Power saving divider LSB.
#define	MCI_RDPROOF   0x00000800
	Enable read proof.
#define	MCI_WRPROOF   0x00001000
	Enable write proof.
#define	MCI_PDCFBYTE   0x00002000
	Force PDC byte transfer.
#define	MCI_PDCPADV   0x00004000
	PDC padding value.
#define	MCI_PDCMODE   0x00008000
	PDC-oriented mode.
#define	MCI_BLKLEN   0xFFFF0000
	Data block length mask.
#define	MCI_BLKLEN_LSB   16
	Data block length LSB.
MMC Data Timeout Register
#define	MCI_DTOR_OFF   0x00000008
	Data timeout register offset.
#define	MCI_DTOR   (MCI_BASE + MCI_DTOR_OFF)
	Data timeout register address.
#define	MCI_DTOCYC   0x0000000F
	Data timeout cycle number mask.
#define	MCI_DTOCYC_LSB   0
	Data timeout cycle number LSB.
#define	MCI_DTOMUL   0x00000070
	Data timeout multiplier mask.
#define	MCI_DTOMUL_1   0x00000000
	Data timeout multiplier 1.
#define	MCI_DTOMUL_16   0x00000010
	Data timeout multiplier 16.
#define	MCI_DTOMUL_128   0x00000020
	Data timeout multiplier 128.
#define	MCI_DTOMUL_256   0x00000030
	Data timeout multiplier 256.
#define	MCI_DTOMUL_1K   0x00000040
	Data timeout multiplier 1024.
#define	MCI_DTOMUL_4K   0x00000050
	Data timeout multiplier 4096.
#define	MCI_DTOMUL_64K   0x00000060
	Data timeout multiplier 65536.
#define	MCI_DTOMUL_1M   0x00000070
	Data timeout multiplier 1048576.
MMC SDCard/SDIO Register
#define	MCI_SDCR_OFF   0x0000000C
	SDC/SDIO register offset.
#define	MCI_SDCR   (MCI_BASE + MCI_SDCR_OFF)
	SDC/SDIO register address.
#define	MCI_SDCSEL   0x00000003
	SDC/SDIO slot mask.
#define	MCI_SDCSEL_SLOTA   0x00000000
	Slot A selected.
#define	MCI_SDCSEL_SLOTB   0x00000001
	Slot B selected.
#define	MCI_SDCBUS   0x00000080
	SDC/SDIO 4-bit bus.
MMC Argument Register
#define	MCI_ARGR_OFF   0x00000010
	Argument register offset.
#define	MCI_ARGR   (MCI_BASE + MCI_ARGR_OFF)
	Argument register address.
MMC Command Register
#define	MCI_CMDR_OFF   0x00000014
	Command register offset.
#define	MCI_CMDR   (MCI_BASE + MCI_CMDR_OFF)
	Command register address.
#define	MCI_CMDNB   0x0000003F
	Command number mask.
#define	MCI_CMDNB_LSB   0
	Command number LSB.
#define	MCI_RSPTYP   0x000000C0
	Response type mask.
#define	MCI_RSPTYP_NONE   0x00000000
	No response.
#define	MCI_RSPTYP_48   0x00000040
	48-bit response
#define	MCI_RSPTYP_136   0x00000080
	136-bit response
#define	MCI_SPCMD   0x00000700
	Special command mask.
#define	MCI_SPCMD_NONE   0x00000000
	Not a special command.
#define	MCI_SPCMD_INIT   0x00000100
	Initialization command.
#define	MCI_SPCMD_SYNC   0x00000200
	Synchronized command.
#define	MCI_SPCMD_ICMD   0x00000400
	Interrupt command.
#define	MCI_SPCMD_IRSP   0x00000500
	Interrupt response.
#define	MCI_OPCMD   0x00000800
	Open drain command.
#define	MCI_MAXLAT   0x00001000
	Maximum latency for command to response.
#define	MCI_TRCMD   0x00030000
	Transfer command mask.
#define	MCI_TRCMD_NONE   0x00000000
	No data transfer.
#define	MCI_TRCMD_START   0x00010000
	Start data transfer.
#define	MCI_TRCMD_STOP   0x00020000
	Stop data transfer.
#define	MCI_TRDIR   0x00040000
	Read transfer.
#define	MCI_TRTYP   0x00380000
	Transfer type mask.
#define	MCI_TRTYP_MMC_SBLK   0x00000000
	MMC/SDC single block transfer.
#define	MCI_TRTYP_MMC_MBLK   0x00080000
	MMC/SDC multiple block transfer.
#define	MCI_TRTYP_MMC_STREAM   0x00100000
	MMC stream transfer.
#define	MCI_TRTYP_SDIO_BYTE   0x00200000
	SDIO byte transfer.
#define	MCI_TRTYP_SDIO_BLK   0x00280000
	SDIO block transfer.
#define	MCI_IOSPCMD   0x03000000
	Specila SDIO command mask.
#define	MCI_IOSPCMD_NONE   0x00000000
	Not a special SDIO command.
#define	MCI_IOSPCMD_SUSPEND   0x01000000
	SDIO suspend command.
#define	MCI_IOSPCMD_RESUME   0x02000000
	SDIO resume command.
MMC Block Register
#define	MCI_BLKR_OFF   0x00000018
	Block register offset.
#define	MCI_BLKR   (MCI_BASE + MCI_BLKR_OFF)
	Block register address.
#define	MCI_BCNT   0x0000FFFF
	MMC/SDIO block count or SDIO byte count mask.
#define	MCI_BCNT_LSB   0
	MMC/SDIO block count or SDIO byte count LSB.
MMC Response Register
#define	MCI_RSPR_OFF   0x00000020
	Response register offset.
#define	MCI_RSPR   (MCI_BASE + MCI_RSPR_OFF)
	Response register address.
MMC Receive Data Register
#define	MCI_RDR_OFF   0x00000030
	Receive data register offset.
#define	MCI_RDR   (MCI_BASE + MCI_RDR_OFF)
	Receive data register address.
MMC Transmit Data Register
#define	MCI_TDR_OFF   0x00000034
	Transmit data register offset.
#define	MCI_TDR   (MCI_BASE + MCI_TDR_OFF)
	Transmit data register address.
MMC Interrupt and Status Registers
#define	MCI_SR_OFF   0x00000040
	Status register offset.
#define	MCI_SR   (MCI_BASE + MCI_SR_OFF)
	Status register address.
#define	MCI_IER_OFF   0x00000044
	Enable register offset.
#define	MCI_IER   (MCI_BASE + MCI_IER_OFF)
	Enable register address.
#define	MCI_IDR_OFF   0x00000048
	Disable register offset.
#define	MCI_IDR   (MCI_BASE + MCI_IDR_OFF)
	Disable register address.
#define	MCI_IMR_OFF   0x0000004C
	Mask register offset.
#define	MCI_IMR   (MCI_BASE + MCI_IMR_OFF)
	Mask register address.
#define	MCI_CMDRDY   0x00000001
	Command ready.
#define	MCI_RXRDY   0x00000002
	Receiver ready.
#define	MCI_TXRDY   0x00000004
	Transmit ready.
#define	MCI_BLKE   0x00000008
	Data block ended.
#define	MCI_DTIP   0x00000010
	Data transfer in progress.
#define	MCI_NOTBUSY   0x00000020
	MCI not busy.
#define	MCI_ENDRX   0x00000040
	End of receive buffer.
#define	MCI_ENDTX   0x00000080
	End of transmit buffer.
#define	MCI_SDIOIRQA   0x00000100
	Undocumented.
#define	MCI_SDIOIRQB   0x00000200
	Undocumented.
#define	MCI_RXBUFF   0x00004000
	Receive buffer full.
#define	MCI_TXBUFE   0x00008000
	Transmit buffer empty.
#define	MCI_RINDE   0x00010000
	Response index error.
#define	MCI_RDIRE   0x00020000
	Response direction error.
#define	MCI_RCRCE   0x00040000
	Response CRC error.
#define	MCI_RENDE   0x00080000
	Response end bit error.
#define	MCI_RTOE   0x00100000
	Response timeout error.
#define	MCI_DCRCE   0x00200000
	Data CRC error.
#define	MCI_DTOE   0x00400000
	Date timeout error.
#define	MCI_OVRE   0x40000000
	Overrun error.
#define	MCI_UNRE   0x80000000
	Underrun error.

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