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MMC Control Register |
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#define | MCI_CR_OFF 0x00000000 |
| | Control register offset.
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#define | MCI_CR (MCI_BASE + MCI_CR_OFF) |
| | Control register address.
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#define | MCI_MCIEN 0x00000001 |
| | Interface enable.
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#define | MCI_MCIDIS 0x00000002 |
| | Interface disable.
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#define | MCI_PWSEN 0x00000004 |
| | Power save mode enable.
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#define | MCI_PWSDIS 0x00000008 |
| | Power save mode disable.
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#define | MCI_SWRST 0x00000080 |
| | Software reset.
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MMC Mode Register |
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#define | MCI_MR_OFF 0x00000004 |
| | Mode register offset.
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#define | MCI_MR (MCI_BASE + MCI_MR_OFF) |
| | Mode register address.
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#define | MCI_CLKDIV 0x000000FF |
| | Clock divider mask.
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#define | MCI_CLKDIV_LSB 0 |
| | Clock divider LSB.
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#define | MCI_PWSDIV 0x00000700 |
| | Power saving divider mask.
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#define | MCI_PWSDIV_LSB 8 |
| | Power saving divider LSB.
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#define | MCI_RDPROOF 0x00000800 |
| | Enable read proof.
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#define | MCI_WRPROOF 0x00001000 |
| | Enable write proof.
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#define | MCI_PDCFBYTE 0x00002000 |
| | Force PDC byte transfer.
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#define | MCI_PDCPADV 0x00004000 |
| | PDC padding value.
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#define | MCI_PDCMODE 0x00008000 |
| | PDC-oriented mode.
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#define | MCI_BLKLEN 0xFFFF0000 |
| | Data block length mask.
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#define | MCI_BLKLEN_LSB 16 |
| | Data block length LSB.
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MMC Data Timeout Register |
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#define | MCI_DTOR_OFF 0x00000008 |
| | Data timeout register offset.
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#define | MCI_DTOR (MCI_BASE + MCI_DTOR_OFF) |
| | Data timeout register address.
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#define | MCI_DTOCYC 0x0000000F |
| | Data timeout cycle number mask.
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#define | MCI_DTOCYC_LSB 0 |
| | Data timeout cycle number LSB.
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#define | MCI_DTOMUL 0x00000070 |
| | Data timeout multiplier mask.
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#define | MCI_DTOMUL_1 0x00000000 |
| | Data timeout multiplier 1.
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#define | MCI_DTOMUL_16 0x00000010 |
| | Data timeout multiplier 16.
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#define | MCI_DTOMUL_128 0x00000020 |
| | Data timeout multiplier 128.
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#define | MCI_DTOMUL_256 0x00000030 |
| | Data timeout multiplier 256.
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#define | MCI_DTOMUL_1K 0x00000040 |
| | Data timeout multiplier 1024.
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#define | MCI_DTOMUL_4K 0x00000050 |
| | Data timeout multiplier 4096.
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#define | MCI_DTOMUL_64K 0x00000060 |
| | Data timeout multiplier 65536.
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#define | MCI_DTOMUL_1M 0x00000070 |
| | Data timeout multiplier 1048576.
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MMC SDCard/SDIO Register |
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#define | MCI_SDCR_OFF 0x0000000C |
| | SDC/SDIO register offset.
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#define | MCI_SDCR (MCI_BASE + MCI_SDCR_OFF) |
| | SDC/SDIO register address.
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#define | MCI_SDCSEL 0x00000003 |
| | SDC/SDIO slot mask.
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#define | MCI_SDCSEL_SLOTA 0x00000000 |
| | Slot A selected.
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#define | MCI_SDCSEL_SLOTB 0x00000001 |
| | Slot B selected.
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#define | MCI_SDCBUS 0x00000080 |
| | SDC/SDIO 4-bit bus.
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MMC Argument Register |
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#define | MCI_ARGR_OFF 0x00000010 |
| | Argument register offset.
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#define | MCI_ARGR (MCI_BASE + MCI_ARGR_OFF) |
| | Argument register address.
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MMC Command Register |
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#define | MCI_CMDR_OFF 0x00000014 |
| | Command register offset.
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#define | MCI_CMDR (MCI_BASE + MCI_CMDR_OFF) |
| | Command register address.
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#define | MCI_CMDNB 0x0000003F |
| | Command number mask.
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#define | MCI_CMDNB_LSB 0 |
| | Command number LSB.
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#define | MCI_RSPTYP 0x000000C0 |
| | Response type mask.
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#define | MCI_RSPTYP_NONE 0x00000000 |
| | No response.
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#define | MCI_RSPTYP_48 0x00000040 |
| | 48-bit response
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#define | MCI_RSPTYP_136 0x00000080 |
| | 136-bit response
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#define | MCI_SPCMD 0x00000700 |
| | Special command mask.
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#define | MCI_SPCMD_NONE 0x00000000 |
| | Not a special command.
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#define | MCI_SPCMD_INIT 0x00000100 |
| | Initialization command.
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#define | MCI_SPCMD_SYNC 0x00000200 |
| | Synchronized command.
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#define | MCI_SPCMD_ICMD 0x00000400 |
| | Interrupt command.
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#define | MCI_SPCMD_IRSP 0x00000500 |
| | Interrupt response.
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#define | MCI_OPCMD 0x00000800 |
| | Open drain command.
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#define | MCI_MAXLAT 0x00001000 |
| | Maximum latency for command to response.
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#define | MCI_TRCMD 0x00030000 |
| | Transfer command mask.
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#define | MCI_TRCMD_NONE 0x00000000 |
| | No data transfer.
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#define | MCI_TRCMD_START 0x00010000 |
| | Start data transfer.
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#define | MCI_TRCMD_STOP 0x00020000 |
| | Stop data transfer.
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#define | MCI_TRDIR 0x00040000 |
| | Read transfer.
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#define | MCI_TRTYP 0x00380000 |
| | Transfer type mask.
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#define | MCI_TRTYP_MMC_SBLK 0x00000000 |
| | MMC/SDC single block transfer.
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#define | MCI_TRTYP_MMC_MBLK 0x00080000 |
| | MMC/SDC multiple block transfer.
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#define | MCI_TRTYP_MMC_STREAM 0x00100000 |
| | MMC stream transfer.
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#define | MCI_TRTYP_SDIO_BYTE 0x00200000 |
| | SDIO byte transfer.
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#define | MCI_TRTYP_SDIO_BLK 0x00280000 |
| | SDIO block transfer.
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#define | MCI_IOSPCMD 0x03000000 |
| | Specila SDIO command mask.
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#define | MCI_IOSPCMD_NONE 0x00000000 |
| | Not a special SDIO command.
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#define | MCI_IOSPCMD_SUSPEND 0x01000000 |
| | SDIO suspend command.
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#define | MCI_IOSPCMD_RESUME 0x02000000 |
| | SDIO resume command.
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MMC Block Register |
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#define | MCI_BLKR_OFF 0x00000018 |
| | Block register offset.
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#define | MCI_BLKR (MCI_BASE + MCI_BLKR_OFF) |
| | Block register address.
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#define | MCI_BCNT 0x0000FFFF |
| | MMC/SDIO block count or SDIO byte count mask.
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#define | MCI_BCNT_LSB 0 |
| | MMC/SDIO block count or SDIO byte count LSB.
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MMC Response Register |
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#define | MCI_RSPR_OFF 0x00000020 |
| | Response register offset.
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#define | MCI_RSPR (MCI_BASE + MCI_RSPR_OFF) |
| | Response register address.
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MMC Receive Data Register |
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#define | MCI_RDR_OFF 0x00000030 |
| | Receive data register offset.
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#define | MCI_RDR (MCI_BASE + MCI_RDR_OFF) |
| | Receive data register address.
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MMC Transmit Data Register |
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#define | MCI_TDR_OFF 0x00000034 |
| | Transmit data register offset.
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#define | MCI_TDR (MCI_BASE + MCI_TDR_OFF) |
| | Transmit data register address.
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MMC Interrupt and Status Registers |
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#define | MCI_SR_OFF 0x00000040 |
| | Status register offset.
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#define | MCI_SR (MCI_BASE + MCI_SR_OFF) |
| | Status register address.
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#define | MCI_IER_OFF 0x00000044 |
| | Enable register offset.
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#define | MCI_IER (MCI_BASE + MCI_IER_OFF) |
| | Enable register address.
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#define | MCI_IDR_OFF 0x00000048 |
| | Disable register offset.
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#define | MCI_IDR (MCI_BASE + MCI_IDR_OFF) |
| | Disable register address.
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#define | MCI_IMR_OFF 0x0000004C |
| | Mask register offset.
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#define | MCI_IMR (MCI_BASE + MCI_IMR_OFF) |
| | Mask register address.
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#define | MCI_CMDRDY 0x00000001 |
| | Command ready.
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#define | MCI_RXRDY 0x00000002 |
| | Receiver ready.
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#define | MCI_TXRDY 0x00000004 |
| | Transmit ready.
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#define | MCI_BLKE 0x00000008 |
| | Data block ended.
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#define | MCI_DTIP 0x00000010 |
| | Data transfer in progress.
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#define | MCI_NOTBUSY 0x00000020 |
| | MCI not busy.
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#define | MCI_ENDRX 0x00000040 |
| | End of receive buffer.
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#define | MCI_ENDTX 0x00000080 |
| | End of transmit buffer.
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#define | MCI_SDIOIRQA 0x00000100 |
| | Undocumented.
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#define | MCI_SDIOIRQB 0x00000200 |
| | Undocumented.
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#define | MCI_RXBUFF 0x00004000 |
| | Receive buffer full.
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#define | MCI_TXBUFE 0x00008000 |
| | Transmit buffer empty.
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#define | MCI_RINDE 0x00010000 |
| | Response index error.
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#define | MCI_RDIRE 0x00020000 |
| | Response direction error.
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#define | MCI_RCRCE 0x00040000 |
| | Response CRC error.
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#define | MCI_RENDE 0x00080000 |
| | Response end bit error.
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#define | MCI_RTOE 0x00100000 |
| | Response timeout error.
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#define | MCI_DCRCE 0x00200000 |
| | Data CRC error.
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#define | MCI_DTOE 0x00400000 |
| | Date timeout error.
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#define | MCI_OVRE 0x40000000 |
| | Overrun error.
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#define | MCI_UNRE 0x80000000 |
| | Underrun error.
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