*
* $Log: at91x40.h,v $
* Revision 1.4 2006/10/08 16:48:09 haraldkipp
* Documentation fixed
*
* Revision 1.3 2006/08/05 11:56:29 haraldkipp
* Old SAM7X leftovers finally removed.
* PDC register configuration added.
*
* Revision 1.2 2006/08/01 07:35:59 haraldkipp
* Exclude function prototypes when included by assembler.
*
* Revision 1.1 2006/07/05 07:45:28 haraldkipp
* Split on-chip interface definitions.
*
* Revision 1.7 2006/06/28 17:22:34 haraldkipp
* Make it compile for AT91SAM7X256.
*
* Revision 1.6 2006/05/25 09:09:57 haraldkipp
* API documentation updated and corrected.
*
* Revision 1.5 2006/04/07 12:57:00 haraldkipp
* Fast interrupt doesn't require to store R8-R12.
*
* Revision 1.4 2006/03/02 20:02:56 haraldkipp
* Added ICCARM interrupt entry code. Probably not working, because I
* excluded an immediate load.
*
* Revision 1.3 2006/01/05 16:52:49 haraldkipp
* Baudrate calculation is now based on NutGetCpuClock().
* The AT91_US_BAUD macro had been marked deprecated.
*
* Revision 1.2 2005/11/20 14:44:14 haraldkipp
* Register offsets added.
*
* Revision 1.1 2005/10/24 10:31:13 haraldkipp
* Moved from parent directory.
*
*
*
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Peripheral Identifiers and Interrupts |
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#define | FIQ_ID 0 |
| | Fast interrupt ID.
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#define | SWIRQ_ID 1 |
| | Software interrupt ID.
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#define | US0_ID 2 |
| | USART 0 ID.
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#define | US1_ID 3 |
| | USART 1 ID.
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#define | TC0_ID 4 |
| | Timer 0 ID.
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#define | TC1_ID 5 |
| | Timer 1 ID.
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#define | TC2_ID 6 |
| | Timer 2 ID.
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#define | WDI_ID 7 |
| | Watchdog interrupt ID.
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#define | PIO_ID 8 |
| | Parallel I/O controller ID.
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#define | IRQ0_ID 16 |
| | External interrupt 0 ID.
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#define | IRQ1_ID 17 |
| | External interrupt 1 ID.
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#define | IRQ2_ID 18 |
| | External interrupt 2 ID.
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Defines |
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#define | EBI_BASE 0xFFE00000 |
| | EBI base address.
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#define | SF_BASE 0xFFF00000 |
| | Special function register base address.
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#define | USART1_BASE 0xFFFCC000 |
| | USART 1 base address.
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#define | USART0_BASE 0xFFFD0000 |
| | USART 0 base address.
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#define | TC_BASE 0xFFFE0000 |
| | TC base address.
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#define | PIO_BASE 0xFFFF0000 |
| | PIO base address.
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#define | PS_BASE 0xFFFF4000 |
| | PS base address.
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#define | WD_BASE 0xFFFF8000 |
| | Watch Dog register base address.
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| #define | AIC_BASE 0xFFFFF000 |
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#define | PERIPH_RPR_OFF 0x00000030 |
| | Receive pointer register offset.
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#define | PERIPH_RCR_OFF 0x00000034 |
| | Receive counter register offset.
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#define | PERIPH_TPR_OFF 0x00000038 |
| | Transmit pointer register offset.
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#define | PERIPH_TCR_OFF 0x0000003C |
| | Transmit counter register offset.
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#define | USART_HAS_PDC |
Functions |
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void | McuInit (void) |
| | AT91 specific initialization.
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