Parallel I/O
[AT91]

Collaboration diagram for Parallel I/O:

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Detailed Description

Parallel I/O controller registers.

Most parallel I/O lines are multiplexed with external signals of other peripherals to optimize the use of available package pins.

PIO Register Offsets
#define	PIO_PER_OFF   0x00000000
	PIO enable register offset.
#define	PIO_PDR_OFF   0x00000004
	PIO disable register offset.
#define	PIO_PSR_OFF   0x00000008
	PIO status register offset.
#define	PIO_OER_OFF   0x00000010
	Output enable register offset.
#define	PIO_ODR_OFF   0x00000014
	Output disable register offset.
#define	PIO_OSR_OFF   0x00000018
	Output status register offset.
#define	PIO_IFER_OFF   0x00000020
	Input filter enable register offset.
#define	PIO_IFDR_OFF   0x00000024
	Input filter disable register offset.
#define	PIO_IFSR_OFF   0x00000028
	Input filter status register offset.
#define	PIO_SODR_OFF   0x00000030
	Set output data register offset.
#define	PIO_CODR_OFF   0x00000034
	Clear output data register offset.
#define	PIO_ODSR_OFF   0x00000038
	Output data status register offset.
#define	PIO_PDSR_OFF   0x0000003C
	Pin data status register offset.
#define	PIO_IER_OFF   0x00000040
	Interrupt enable register offset.
#define	PIO_IDR_OFF   0x00000044
	Interrupt disable register offset.
#define	PIO_IMR_OFF   0x00000048
	Interrupt mask register offset.
#define	PIO_ISR_OFF   0x0000004C
	Interrupt status register offset.

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