XgNutArchArmAt91Rstc

Reset Controller Control Register
#define	RSTC_CR   (RSTC_BASE + 0x00)
	Reset controller control register address.
#define	RSTC_PROCRST   0x00000001
	Processor reset.
#define	RSTC_PERRST   0x00000004
	Peripheral reset.
#define	RSTC_EXTRST   0x00000008
	External reset.
#define	RSTC_KEY   0xA5000000
	Password.
Reset Controller Status Register
#define	RSTC_SR   (RSTC_BASE + 0x04)
	Reset controller status register address.
#define	RSTC_URSTS   0x00000001
	User reset status.
#define	RSTC_BODSTS   0x00000002
	Brownout detection status.
#define	RSTC_RSTTYP   0x00000700
	Reset type.
#define	RSTC_RSTTYP_POWERUP   0x00000000
	Power-up reset.
#define	RSTC_RSTTYP_WAKEUP   0x00000100
	VDDCORE rising.
#define	RSTC_RSTTYP_WATCHDOG   0x00000200
	Watchdog reset.
#define	RSTC_RSTTYP_SOFTWARE   0x00000300
	Software reset.
#define	RSTC_RSTTYP_USER   0x00000400
	User reset.
#define	RSTC_RSTTYP_BROWNOUT   0x00000500
	Brownout reset.
#define	RSTC_NRSTL   0x00010000
	NRST pin level.
#define	RSTC_SRCMP   0x00020000
	Software reset command in progress.
Reset Controller Mode Register
#define	RSTC_MR   (RSTC_BASE + 0x08)
	Reset controller mode register address.
#define	RSTC_URSTEN   0x00000001
	User reset enable.
#define	RSTC_URSTIEN   0x00000010
	User reset interrupt enable.
#define	RSTC_ERSTL   0x00000F00
	External reset length.
#define	RSTC_ERSTL_LSB   8
	Least significant bit of external reset length.
#define	RSTC_BODIEN   0x00010000
	Brown-out detection interrupt enable.

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