Collaboration diagram for VLSI VS1001K:
Data Structures | |
struct | VS_HEADERINFO |
Defines | |
#define | VS_OPCODE_READ 3 |
#define | VS_OPCODE_WRITE 2 |
#define | VS_MODE_REG 0 |
#define | VS_STATUS_REG 1 |
#define | VS_INT_FCTLH_REG 2 |
#define | VS_CLOCKF_REG 3 |
#define | VS_DECODE_TIME_REG 4 |
#define | VS_AUDATA_REG 5 |
#define | VS_WRAM_REG 6 |
#define | VS_WRAMADDR_REG 7 |
#define | VS_HDAT0_REG 8 |
#define | VS_HDAT1_REG 9 |
#define | VS_A1ADDR_REG 10 |
#define | VS_VOL_REG 11 |
#define | VS_A1CTRL_REG 13 |
#define | VS_SM_DIFF 0x0001 |
#define | VS_SM_FFWD 0x0002 |
#define | VS_SM_RESET 0x0004 |
#define | VS_SM_MP12 0x0008 |
#define | VS_SM_PDOWN 0x0010 |
#define | VS_SM_DAC 0x0020 |
#define | VS_SM_DACMONO 0x0040 |
#define | VS_SM_BASS 0x0080 |
#define | VS_SM_DACT 0x0100 |
#define | VS_SM_BYTEORD 0x0200 |
#define | VS_SM_IBMODE 0x0400 |
#define | VS_SM_IBCLK 0x0800 |
#define | VS_CF_DOUBLER 0x8000 |
#define | VS_FLUSH_BYTES 2048 |
#define | VS_STATUS_STOPPED 0 |
#define | VS_STATUS_RUNNING 1 |
#define | VS_STATUS_EOF 2 |
#define | VS_STATUS_EMPTY 4 |
#define | VS_SCK_BIT 0 |
VS1001 serial control interface clock input bit. | |
#define | VS_SCK_PORT PORTB |
#define | VS_SCK_DDR DDRB |
#define | VS_SS_BIT 1 |
VS1001 serial data interface clock input bit. | |
#define | VS_SS_PORT PORTB |
#define | VS_SS_DDR DDRB |
#define | VS_SI_BIT 2 |
VS1001 serial control interface data input. | |
#define | VS_SI_PORT PORTB |
#define | VS_SI_DDR DDRB |
#define | VS_SO_BIT 3 |
VS1001 serial control interface data output. | |
#define | VS_SO_PIN PINB |
#define | VS_SO_DDR DDRB |
#define | VS_XCS_BIT 4 |
VS1001 active low chip select input. | |
#define | VS_XCS_PORT PORTB |
#define | VS_XCS_DDR DDRB |
#define | VS_BSYNC_BIT 5 |
VS1001 serial data interface bit sync. | |
#define | VS_BSYNC_PORT PORTB |
#define | VS_BSYNC_DDR DDRB |
#define | VS_RESET_BIT 7 |
VS1001 hardware reset input. | |
#define | VS_RESET_PORT PORTB |
#define | VS_RESET_DDR DDRB |
#define | VS_SIGNAL sig_INTERRUPT6 |
VS1001 data request interrupt. | |
#define | VS_DREQ_BIT 6 |
#define | VS_DREQ_PORT PORTE |
#define | VS_DREQ_PIN PINE |
#define | VS_DREQ_DDR DDRE |
Functions | |
int | VsPlayerInit (void) |
Initialize the VS1001 hardware interface. | |
int | VsPlayerReset (u_short mode) |
Software reset the decoder. | |
int | VsPlayerSetMode (u_short mode) |
Set mode register of the decoder. | |
int | VsPlayerKick (void) |
Start playback. | |
int | VsPlayerStop (void) |
Stops the playback. | |
int | VsPlayerFlush (void) |
Sets up decoder internal buffer flushing. | |
u_char | VsPlayerInterrupts (u_char enable) |
Enable or disable player interrupts. | |
u_char * | VsBufferInit (u_short size) |
u_char * | VsBufferReset (void) |
u_char * | VsBufferRequest (u_short *sizep) |
u_char * | VsBufferAcknowledge (u_short nbytes) |
u_short | VsBufferAvailable (void) |
u_short | VsPlayTime (void) |
Returns play time since last reset. | |
u_char | VsGetStatus (void) |
Returns status of the player. | |
int | VsGetHeaderInfo (VS_HEADERINFO *vshi) |
Query MP3 stream header information. | |
u_short | VsMemoryTest (void) |
Initialize decoder memory test and return result. | |
int | VsSetVolume (u_char left, u_char right) |
Set volume. | |
int | VsBeep (u_char fsin, u_char ms) |
Sine wave beep. |
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VS1001 serial control interface clock input bit. The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder. |
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Port register of VS_SCK_BIT. |
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Data direction register of VS_SCK_BIT. |
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Port output register of VS_SS_BIT. |
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Data direction register of VS_SS_BIT. |
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VS1001 serial control interface data input. The decoder samples this input on the rising edge of SCK if XCS is low. |
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Port output register of VS_SI_BIT. |
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Data direction register of VS_SI_BIT. |
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VS1001 serial control interface data output. If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state. |
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Port input register of VS_SO_BIT. |
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Data direction register of VS_SO_BIT. |
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VS1001 active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. |
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Port output register of VS_XCS_BIT. |
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Data direction register of VS_XCS_BIT. |
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VS1001 serial data interface bit sync. The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte. |
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Port output register of VS_BSYNC_BIT. |
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Data direction register of VS_BSYNC_BIT. |
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Port output register of VS_RESET_BIT. |
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Data direction register of VS_RESET_BIT. |
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Port output register of VS_DREQ_BIT. |
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Port input register of VS_DREQ_BIT. |
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Data direction register of VS_DREQ_BIT. |
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Initialize the VS1001 hardware interface.
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Software reset the decoder. This function is typically called after VsPlayerInit() and at the end of each track.
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Set mode register of the decoder.
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Start playback. This routine will send the first MP3 data bytes to the decoder, until it is completely filled. The data buffer should have been filled before calling this routine. Decoder interrupts will be enabled.
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Stops the playback. This routine will stops the MP3 playback, VsPlayerKick() may be used to resume the playback.
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Sets up decoder internal buffer flushing. This routine will set up internal VS buffer flushing, unless the buffer is already empty and starts the playback if necessary. The internal VS buffer is flushed in VsPlayerFeed() at the end of the stream. Decoder interrupts will be enabled.
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Enable or disable player interrupts. This routine is typically used by applications when dealing with unprotected buffers.
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Returns play time since last reset.
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Returns status of the player.
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Query MP3 stream header information.
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Initialize decoder memory test and return result.
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Set volume.
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Sine wave beep.
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